The present disclosure relates generally to metrology for chemical mechanical polishing, and more particularly to systems and methods for eddy current metrology.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the non-planar surface is exposed. For example, a conductive filler layer can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. The filler layer is then polished until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate. In addition, planarization is generally needed to planarize the substrate surface for photolithography.
Chemical mechanical polishing (CMP) is one accepted method of planarization. Conventionally, this planarization method involves holding a substrate on with a carrier head and placing the substrate against a rotating polishing pad. The carrier head provides a controllable load on the substrate to push it against the polishing pad. The polishing pad can be either a “standard” pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. A polishing solution, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad (also, some processes use “abrasiveless” polishing).
One problem in CMP is determining whether the polishing process is complete, i.e., whether a substrate layer has been planarized to a desired flatness or thickness, or when a desired amount of material has been removed, or whether an underlying layer has been exposed. Overpolishing (removing too much) of a conductive layer or film leads to increased circuit resistance. On the other hand, underpolishing (removing too little) of a conductive layer leads to electrical shorting. Variations in the initial thickness of the substrate layer, the slurry composition, the polishing pad condition, the relative speed between the polishing pad and the substrate, and the load on the substrate can cause variations in the material removal rate. These variations cause variations in the time needed to reach the polishing endpoint. Therefore, the polishing endpoint cannot be determined merely as a function of polishing time.
Two techniques are used to compensate for variations in the polishing endpoint. In-line metrology systems measure the thickness of layers on the substrate before and after processing. Assuming the layer thickness is determined prior to polishing, the polishing time can be adjusted to provide more accurate control of the amount of material remaining on the substrate after polishing. In-situ systems monitor the substrate during polishing to measure the amount of material removed or to detect sudden changes in substrate characteristics that indicate that a layer has been exposed.
A recent in-situ endpoint detection technique induces an eddy current in a metal layer on the substrate and uses an eddy current sensor to monitor the change in the eddy current as the metal layer is removed.